1. Field of the Invention
The invention relates to a data memory circuit having a multiplicity of addressable memory cells, a command decoding device for decoding external commands and a control device for controlling or initiating operations for the operation of the memory circuit in each case in a manner dependent on the decoded commands. One area of application of the invention is that of DRAMs (Dynamic Random Access Memories), i.e., dynamic read-write memories with the possibility of direct access to the memory cells.
2. Description of the Related Art
The operation of a data memory circuit includes, above all, the writing in and reading-out of data at selectively addressed memory cells. A write or read access consists, in principle, producing a data connection between the respectively addressed memory cells and the data terminals of the memory circuit, which usually comprises closing selected electronic switches in a network of control and data lines which covers the entire array of memory cells. Each write or read process comprises a sequence of individual operations, and in most conventional memory circuits the relevant operation commands are applied by an external controller. The controller generally “knows” the specification of the memory circuit and thus “knows” from the outset how long the execution of an operation command lasts and accordingly how long to wait before being permitted to send a new command which ends the previously commanded operation.
It can happen, however, that the controller is not exactly coordinated with the specification of the memory circuit and sends a new command early. In this case, the new command must not be obeyed, at least not when the newly commanded operation depends on the successful execution of the previous operation.
Furthermore, in many memory circuits there are certain operating sequences which are initiated by the controller by means of a command and then proceed as an internal self-controlled process, e.g., under the influence of an internal clock signal, without synchronization with the controller. This may involve processes which, although permitted to be interrupted by a new command, must not be interrupted during specific critical phases while proceeding. Since the controller does not know or cannot know when precisely the aforesaid critical phases exist, it is possible for a new command to coincide temporally with such a phase. In this case, too, the new command must not be obeyed. One example of such self-controlled processes is the “self-controlled refresh” of data (self-timed refresh) in DRAMs.
In the case of DRAMs, the memory cells are arranged within individual arrays or segments in each case in matrix form in rows and columns. Each row is assigned a control line referred to as a “word line”, and each column is assigned a so-called “bit line”, which usually has two cores and leads to an amplifier assigned to the relevant column. These amplifiers are referred to as “sense amplifiers”, although they amplify not only data to be read out but also data to be written in. Access to a cell is begun by activation of the relevant word line in accordance with a row address, as a result of which switches are closed (i.e., turned on) at all cells of the assigned row in order to connect said cells to the sense amplifiers via the bit lines. During this operation, the charge of the cells is discharged onto the bit lines, which until then have been connected to a common “precharge potential”. On account of the discharging of the cell charge, the potential of one bit-line core increases or decreases in each case with respect to the other bit line core which remains at the precharge potential. The sense amplifiers detect the respective potential differences of the bit line pairs and amplify these differences, so that the bit line core having the lower potential is brought to the “low” (ground) potential “L” and the bit line core having the higher potential is brought to the “high” supply potential “H” of the memory cell array. As a result of this, the information sensed at the cells is written back in amplified fashion to the cells and thus refreshed.
In the actual reading or writing mode, after the activation operation described above, the sense amplifiers are selectively connected to the data terminals of the DRAM under control through column address information. In the event of reading, the data latched in the sense amplifiers are taken at the data terminals; for the purpose of writing, the data latched in the sense amplifiers are overwritten by the new data input at the data terminals and are thus transferred into the memory cells via the bit lines.
Since the cells lose their charge and thus the information stored in them in each case after a relatively short time, they have to be periodically refreshed between the read or write accesses. For this purpose, all the word lines of the DRAM have to be activated successively at suitable time intervals in order to cause the sensed cell information to be written back in amplified fashion as described above. After the cell information has been refreshed in this way, the relevant word line is brought to the non-active normal state again, as a result of which the bit line cores are electrically insulated from the memory cells. If this has been done, then both bit line cores are brought to the common precharge potential again (“precharge” state). The entire operation of word line activation and bit line amplification by the sense amplifier takes up a certain minimum time described by the specification parameter tRAS. If this time is shortened, for instance by virtue of the internal “precharge” of the bit lines being executed too early, then the full charge state of the cells cannot be reestablished. In the extreme case, the cell information may in this way even be attenuated instead of refreshed. In order to preclude this risk, a tRAS timer is activated during the word line activation, which timer instigates the execution of the precharge only when the full charge state of the cells is established. This waiting time thus signifies a critical operating state of the DRAM during which specific external commands are to be regarded as impermissible because it would be impermissible to execute them at this time.
During regular useful operation of the DRAM, the external controller coordinates the refresh cycles with the write and read cycles, for instance, by sending an “auto refresh” command between writing and reading operations, in order to activate an internal refresh counter which is synchronized with the controller by means of the common system clock and controls the cyclic activation of the word lines for the refresh. On account of this synchronization and with knowledge of the specification of the DRAM, the controller can avoid the situation in which its next command (e.g., the external activation command upon resumption of a write or read cycle) falls within the running time of the tRAS timer.
The situation is different, however, in the case of the self-timed refresh. This operation is carried out during relatively long quiescent times of the DRAM. For this purpose, the cell information refresh controlled by the DRAM is initiated once by an external command of the controller, usually by zeroing its output signal CKE (“clock enable”) with simultaneous issuing of the auto refresh command. The DRAM remains in this state as long as the external signal CKE retains the logic value 0. During this time, a self-refresh timing device runs in the DRAM under the influence of an internal oscillator and controls the sequential activation of the word lines without external action. This sequence remains hidden to the controller. If CKE is brought to a logic 1 by the controller, the DRAM leaves the self-timed refresh state. However, if there is a word line refresh underway at this time, the precharge is delayed by the tRAS timer until the complete refresh of the corresponding memory cells is ensured. If, during this time, the controller directs one of the impermissible commands to the DRAM (e.g., activation of another word line), then the execution of this command is blocked in the DRAM, and the command is rejected. This command refusal is effected on the basis of a status indication indicating that the time determined by the tRAS timer has not yet elapsed.
The above-described self-timed refresh in a DRAM is only an illustrative example of processes or operations which are intended to proceed in a data memory and are not permitted to be terminated or disturbed at any time by any arbitrary external command. It depends on the respective type of data memory as to what processes of this type are taken into consideration for this and what external commands are respectively impermissible. In any event, however, the rejection of external commands at a data memory circuit may lead to serious disturbances in the entire system in which the memory circuit is situated.